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Lichee Tang Premier

Wiki for Sipeed

Pinout

Pin K14 is a 24Mhz clock. FPGA reference for board is EG4S20BG256

Exemple of .adc constrain pins file :

set_pin_assignment {clk_24} { LOCATION = K14; }   ##24MHZ
set_pin_assignment {reset} { LOCATION = K16; }    ##USER_KEY
set_pin_assignment {H} { LOCATION = M12;  }
set_pin_assignment {V} { LOCATION = R16;  }
set_pin_assignment {Rout} { LOCATION = N12;  }
set_pin_assignment {Gout} { LOCATION = P12;  }
set_pin_assignment {Bout} { LOCATION = N11;  }

Dev env

Anlogic TD

Anlogic TD can be download here : Sipeed - /TANG/Premier/IDE/. If you have problem with licence key, download latest release (or hack )

Work with VHDL and Verilog, juste click Generate Bitstreamon bottom left will generate bitstream and you can download to fpga with download (add file then run in the new windows)

Generate clock IP with PLL

Inside Tools->IP generator, create a new IP core, name it and check Simultaneaously create VHDL file if you use VHDL. Choose your IP type, here Phase Locked Loop - PLL -> PLL. Change input frequency to 24Mhz (since it’s all we have), and configure as you want. Click next, select what you need, then next. Configure your clocks, clock division factor and multiplication factor are show on the top. Next and OK, then add IP file (verilog or vhdl).